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| PJ4812 25V Dual N-Channel Enhancement Mode MOSFET FEATURES * RDS(ON), VGS@10V,IDS@5.8A=15m * RDS(ON), VGS@4.5V,IDS@4.7A=24m * Advanced Trench Process Technology * High Density Cell Design For Ultra Low On-Resistance * Specially Designed for DC/DC Converters * Fully Characterized Avalanche Voltage and Current * Pb free product : 99% Sn above can meet RoHS environment substance directive request SOIC-08 MECHANICALDATA * Case: SOIC-08 Package * Terminals : Solderable per MIL-STD-750,Method 2026 * Marking : 4812 8 7 6 5 PIN Assignment 1. Source 1 2. Gate 1 3. Source 2 4. Gate 2 5. Drain 2 6. Drain 2 7. Drain 1 8. Drain 1 1 2 3 4 Maximum RATINGS and Thermal Characteristics (TA=25OC unless otherwise noted ) PA RA M E TE R D r a i n- S o ur c e Vo l t a g e G a t e - S o ur c e Vo l t a g e C o nt i nuo us D r a i n C ur r e nt P ul s e d D r a i n C ur r e nt 1) S ym b o l VD S VGS ID ID M TA = 2 5 O C TA = 7 5 O C PD TJ , TS T G EAS RJ A Li mi t 25 +20 5 .8 24 2 .0 1 .2 -5 5 to + 1 5 0 130 6 2 .5 U ni t s V V A A W O M a xi m um P o w e r D i s s i p a t i o n O p e r a t i n g J u n c t i o n a n d S t o r a g e Te m p e r a t u r e R a n g e Avalanche Energy with Single Pulse ID=23A, VDD=25V, L=0.5mH Junction-to Ambient Thermal Resistance(PCB mounted)2 C mJ O C /W Note: 1. Maximum DC current limited by the package 2. Surface mounted on FR4 board, t < 10 sec PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE STAD-JUL.19.2006 PAGE . 1 PJ4812 ELECTRICALCHARACTERISTICS P a ra me te r S ta ti c D r a i n- S o ur c e B r e a k d o w n Vo l t a g e G a t e Thr e s ho l d Vo l t a g e D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e Ze r o G a t e Vo l t a g e D r a i n C ur r e nt Gate Body Leakage Forward Transconductance Dynamic V D S = 1 5 V , ID = 5 . 8 A , V G S = 5 V To t a l G a t e C h a r g e Qg G a t e - S o ur c e C ha r g e G a t e - D r a i n C ha r g e Tu r n - O n D e l a y Ti m e Tu r n - O n R i s e Ti m e Tu r n - O f f D e l a y Ti m e Tu r n - O f f F a l l Ti m e In p u t C a p a c i t a n c e O ut p ut C a p a c i t a nc e R e v e r s e Tr a n s f e r C a p a c i t a n c e S o ur c e - D r a i n D i o d e M a x. D i o d e F o r w a r d C ur r e nt D i o d e F o rwa rd Vo lta g e Is VSD IS = 1 . 7 A , V G S = 0 V 0 .7 3 1 .7 1 .2 A V Qg s Qg d Td ( o n ) trr td (o ff) tf Ciss Coss C rs s V D S =1 5 V, V G S =0 V f=1 .0 MHZ VD D =15V , RL =15 ID =1A , VG E N =10V RG =3.6 V D S = 1 5 V , ID = 5 . 8 A V G S =10V 2 6 .8 5 .0 5 .5 12 10 32 6 .5 1450 260 150 nC 14 12.5 ns 3 7 .5 8 pF 1 5 .8 BVD SS V G S (th) RD S (o n) RD S (o n) ID S S IG S S g fS V G S = 0 V , ID = 2 5 0 u A V D S = V G S , ID = 2 5 0 u A VG S =4.5V, ID =4.7A VG S =10V, ID =5.8A VD S =25V, VG S =0V V G S =+2 0 V, V D S =0 V V D S = 1 0 V , ID = 5 . 8 A 25 1 20 1 9 .8 12.0 3 2 4 .0 m 15.0 1 +100 uA nA S V V S ym b o l Te s t C o n d i t i o n M i n. Ty p . M a x. U ni t s Switching Test Circuit VIN VDD RL VOUT Gate Charge Test Circuit VGS VDD RL RG 1mA RG STAD-JUL.19.2006 PAGE . 2 PJ4812 Typical Characteristics Curves (TA=25 C,unless otherwise noted) O ID - Drain-to-Source Current (A) 40 ID - Drain Source Current (A) 40 V GS =10V, 6.0V, 5.0, 4.5V V DS=10V 30 4.0V 30 20 3.5V 3.0V 2.5V 20 T J=125 OC 10 10 T J=-55 OC T J=25 OC 0 0 1 2 3 4 5 0 1.5 2 2.5 3 3.5 4 4.5 5 VDS - Drain-to-Source Voltage (V) V GS - Gate-to-Source Voltage (V) Fig. 1-TYPICAL FORWARD CHARACTERISTIC FIG.1- Output Characteristic FIG.2- Transfer Characteristic 60 35 R DS(ON) - On-Resistance (m W ) 30 25 20 15 10 5 0 R DS(ON) - On-Resistance (m W ) I D=5.8A 50 40 30 20 10 0 V GS=4.5V V GS=10V T J=125 OC T J=25 OC 2 4 6 8 10 0 10 20 30 40 ID - Drain Current (A) V GS - Gate-to-Source Voltage (V) FIG.3- On Resistance vs Drain Current 1.4 FIG.4- On Resistance vs Gate to Source Voltage 2000 RDS(ON) - On-Resistance(Normalized) C - Capacitance (pF) V GS=10V 1.3 I D =5.8A 1.2 1.1 1 1750 1500 1250 1000 750 500 250 0 Ciss Ciss V GS=0V f=1MH Z 0.9 0.8 -50 Coss Coss Crss Crss 0 5 10 15 20 25 -25 0 25 50 75 100 125 150 o TJ - Junction Temperature (C) VDS - Drain-to-Source Voltage (V) FIG.5- On Resistance vs Junction Temperature FIG.6- Capacitance STAD-JUL.19.2006 PAGE . 3 PJ4812 10 V GS - Gate-to-Source Voltage (V) Vgs Qg 8 6 4 2 0 V DS=15V I D=5.8A Vgs(th) Qg(th) Qgs Qsw 0 5 10 15 20 25 30 Qgd Qg Qg - Gate Charge (nC) Fig.7 - Gate Charge Waveform Vth - G-S Threshold Voltage (NORMALIZED) Fig.8 - Gate Charge 33 32 31 30 29 28 -50 BVDSS - Breakdown Voltage (V) 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 I D=250uA I D=250uA -25 0 25 50 75 100 125 150 o -25 0 25 50 75 100 125 150 TJ - Junction Temperature (C) TJ - Junction Temperature o(C) Fig.9 - Threshold Voltage vs Temperature Fig.10 - Breakdown Voltage vs Junction Temperature 100 V GS=0V IS - Source Current (A) 10 1 T J=125 OC T J=25 OC T J=-55 OC 0.1 0.01 0.2 0.4 0.6 0.8 1 1.2 1.4 VSD - Source-to-Drain Voltage (V) Fig.11 - Source-Drain Diode Forward Voltage STAD-JUL.19.2006 PAGE . 4 PJ4812 MOUNTING PAD LAYOUT ORDER INFORMATION * Packing information T/R - 3K per 13" plastic Reel LEGALSTATEMENT Copyright PanJit International, Inc 2006 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. STAD-JUL.19.2006 PAGE . 5 |
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